FIELD: computer engineering; interfaces. SUBSTANCE: adapter has ten-bit port address decoder, sixteen-bit ISA bus data writing register, sixteen-bit ISA bus data reading register, Q bus address shaper, first AND gate, and Q bus control signal shaper, as well as first, second, third, and fourth flip-flops, two resistors, first, second, third, fourth, and fifth delay lines, second and third AND gates. EFFECT: provision for interfacing these two buses. 1 cl, 2 dwg
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