FIELD: pulse engineering.
SUBSTANCE: proposed flip-flop device has clocked bistable D flip-flops 1, 2, switches 3, 4, 14, resistors 5, 6, 7, 8, capacitors 9, 10, EXCLUSIVE OR gate 11, NAND gates 12, 21, 22, NOR gate 13, inverters 15, 16, countable signal bus 17, output buses 18, 19, and control bus 20. External noise immunity of device is attained due to eliminating capacitor recharge during arrival of countable signals and operation in univariante ternary code, that is due to change-over of flip-flop device in case of overflow from tracking to subtraction mode and vice versa.
EFFECT: enhanced noise immunity and ability of operation in univariante ternary code.
1 cl, 1 dwg
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Authors
Dates
2005-04-20—Published
2003-09-22—Filed