ACCELERATED MULTIPLIER UNIT BASED ON NEURONS Russian patent published in 2008 - IPC G06F7/52 

Abstract RU 2322688 C2

FIELD: computer engineering, possible use for synthesis of arithmetical and logical devices, for creating fast action and highly productive digital devices which realize the function of multiplication in direct codes.

SUBSTANCE: multiplier contains data input block, multiplicand register block, multiplier register block, addition block, decoder block, result storage block, control block. In multiplier unit, multiplication of binary numbers is performed. The sign of result of multiplication is determined by modulo two addition of signs of multiplicand and multiplier. The operation of multiplication is realized by analyzing lower bits of multiplier, shifting the multiplier for two bits to the right, shifting the multiplicand to the left. The result of multiplication of numbers is produced as a total of partial results of multiplication.

EFFECT: increased speed of operation, increased reliability of operation, simplification of algorithm of operation of device control block.

11 dwg

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RU 2 322 688 C2

Authors

Kobelev Nikolaj Sergeevich

Lopin Vjacheslav Nikolaevich

Kobelev Vladimir Nikolaevich

Sheveleva Elena Sergeevna

Fetisova Evgenija Vladimirovna

Shevelev Sergej Stepanovich

Dates

2008-04-20Published

2006-04-03Filed