FIELD: information technology.
SUBSTANCE: present invention relates to poly-nuclear architecture processors. The device contains at least two execution units which are in form of arithmetic-logic devices (ALU A, ALU B), operating at a given clock frequency, a control unit, connected to the arithmetic-logic devices and to extra units for inputting operands and interacting with the units for inputting operands such that, similar operands are input into two arithmetic-logic devices when operating in the first mode. Different operands are input into two arithmetic-logic devices when operating in the second mode. The control unit can control both arithmetic-logic devices when processing operands in the first mode using similar control signals, and using different control signals when processing operands in the second mode. There is a switching processor between the first and second modes of operation.
EFFECT: more functional capabilities of the device due to operation of the processor in combined mode.
21 cl, 5 dwg
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Authors
Dates
2009-06-27—Published
2004-08-07—Filed