FIELD: physics.
SUBSTANCE: in the known analogue-to-digital converter circuit which includes a differential amplifier (DA), a timed latching device (TLD) at the output of the differential amplifier, a counter at the output of the timed latching device, a first memory capacitor (MC) for recording errors a the input of the differential amplifier, connected by the first terminal to a signal source and by the second to the inverting input of the differential amplifier, a switch connecting the output of the differential amplifier to its inverting input in the on-state, a circuit for generating a linear stepwise rising signal (CGLSRS), proposal is made to include three switches, a reference voltage source and a second memory capacitor whose first terminal is connected to the inverting input of the differential amplifier, and the switches are respectively connected as follows: the first switch is connected to the second terminal of the first memory capacitor and the inverting input of the differential amplifier, the second switch is connected to the output of the differential amplifier and the second terminal of the second memory capacitor, the third switch is connected to the second terminal of the second memory capacitor and the circuit for generating a linear stepwise rising signal, and the non-inverting input of the differential amplifier is connected to the reference voltage source.
EFFECT: preserving accuracy of compensation when switching the analogue-to-digital converter on several signal sources with parasitic potential biasing.
2 dwg
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Authors
Dates
2010-01-27—Published
2007-12-06—Filed