FIELD: information technology.
SUBSTANCE: decoder is designed for use in high-speed television systems which work on the DVB-T standard, and hardware implementation on programmable logic or integrated circuits. The decoder consists of series-connected metric calculation unit, a summation-comparison-selection unit, a transition memory unit, a unit for reconstructing code combinations and code combination memory, series-connected code combination selection unit and delay unit, and an output demultiplexer. The output of the summation-comparison-selection unit is connected to the input of the code combination selection unit. The output of the code combination memory is connected to the data input of the output demultiplexer, and the output of the delay unit is connected to the address input of the output demultiplexer.
EFFECT: improved noise immunity of the decoder and faster information processing.
9 dwg
| Title | Year | Author | Number |
|---|---|---|---|
| CONVOLUTION CODE DECODER | 0 |
|
SU1319283A1 |
| DEVICE FOR COMPUTATION OF METRICS OF PATHS OF VITERBI DECODER | 1990 |
|
RU2022473C1 |
| 0 |
|
SU1777243A1 | |
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|
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|
RU2247471C2 |
| DEVICE FOR DECODING OF CONVOLUTION CODE | 0 |
|
SU1839281A1 |
| CONVOLUTION CODE DECODER | 0 |
|
SU1660178A1 |
