FIELD: electricity.
SUBSTANCE: device comprises field transistors of P-type from the first to the ninth one, field transistors of N-type from the tenth to the eighteenth one, inputs of summands A and B, input of transfer Cin, supply outputs of high and low voltage levels, the first inverter, the output of which is the output of the transfer Cout signal, the second inverter, the output of which is the output of the summing result S, the third inverter and the double-input logical element EXCLUDING-OR.
EFFECT: increased reliability and reduction of adder dimensions.
1 dwg, 1 tbl
| Title | Year | Author | Number |
|---|---|---|---|
| SINGLE-DIGIT BINARY SUMMATOR | 2009 |
|
RU2408922C1 |
| SINGLE-BIT ADDER | 2009 |
|
RU2408058C2 |
| ADDER | 2010 |
|
RU2435196C1 |
| ACCUMULATOR | 2008 |
|
RU2380739C1 |
| SINGLE-BIT BINARY ADDER | 2011 |
|
RU2450324C1 |
| ADDER | 2011 |
|
RU2455680C1 |
| ADDER | 2011 |
|
RU2469381C1 |
| FULL ADDER | 2011 |
|
RU2475811C1 |
| SINGLE-BIT BINARY CMOS ADDER | 2011 |
|
RU2454703C1 |
| MULTIDIGIT ADDER ON SHORT-CHANNEL MIS TRANSISTORS | 2003 |
|
RU2239227C1 |
