FIELD: radio engineering.
SUBSTANCE: device includes five registers (1, 2, 3, 4, 5), (K+7) arithmetic logic devices (91-9k, 6, 8, 10, 13, 15, 20, 22), two adder units (7, 18), (K+3) comparator units (111-11k, 14, 34, 36), (K+4) latch registers (121-12k, 16, 17, 19, 21), (M+1) probabilistic arithmetic logic devices (231-23M+1); M code arithmetic logic devices (241-24M), M probabilistic comparator units (251-25M), M code comparator units (261-26M), (M+1) code latch registers (272-27M+1), (K+3) decoders (291-29k, 28, 30, 31), M probabilistic decoders (321-32M), M code decoders (331-33M), and two demultiplexers (35, 37).
EFFECT: increasing data transfer validity owing to minimising the action of natural and intentional interference on the equipment.
2 dwg
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Authors
Dates
2012-03-27—Published
2011-03-30—Filed