CONTROLLED DELAY LINE Russian patent published in 2012 - IPC H03K5/00 

FIELD: information technology.

SUBSTANCE: delay line has n two-input multiplexers, n outputs of which are connected to n ROM address data sampling inputs, an n-bit ROM data write address binary counter with n inputs for setting the code of the given controlled delay value, an n-bit ROM data read address binary counter with n inputs for setting the code of the given controlled delay value, wherein the first inputs of the n two-input multiplexers are respectively connected to n outputs of the ROM data write address binary counter, and the second inputs of the n two-input multiplexers are respectively connected to n outputs of the ROM data read address binary counter. Control inputs of the n two-input multiplexers are combined and connected to the output of a variable-ratio divider, the same output also being connected to the complementing inputs of the ROM data read/write address binary counters. Variable-ratio divider leads which control the division ratio determine the required delay line control discrete value.

EFFECT: broader functional capabilities of the delay line by controlling the speed of the incoming information stream towards its increasing or decreasing side.

3 cl, 2 dwg