FIELD: electricity.
SUBSTANCE: measurement of voltages at the outlet UOUT and the inlet of UIN of a PVS, throttle It and load Il current of the PVS is carried out at each period of transformation into fixed moments of time (mT+τ). The measured voltage values UOUT and UIN, currents It and IL are memorised. A signal "capacitor current" Ic =It-Il-UOUT/UIN is calculated, as well as a mismatch signal ε=UOUT-UIN, where Uref - reference voltage. From the value of the signal "capacitor current" Ic(mT+τ) the value of "capacitor current" signal is subtracted as Ic((m-1)T+τ), memorised at the previous stage, and the value of "capacitor current" signal is memorised as produced at the current stage of transformation. The mismatch signal 6 is increased KT times, and its finite-different summation is carried out. The "capacitor current" signal is exposed to frequency correction, and summed up with a mismatch signal is sent to an inlet of a pulse-width modulator.
EFFECT: higher quality of output voltage of a pulse DC voltage stabiliser with a power circuit of step-up type.
9 dwg
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Authors
Dates
2012-08-27—Published
2011-07-22—Filed