APPARATUS AND METHODS FOR FREQUENCY CONTROL IN MULTI-OUTPUT FREQUENCY SYNTHESISER Russian patent published in 2013 - IPC H03L7/16 H03J7/06 

FIELD: radio engineering, communication.

SUBSTANCE: methods and circuits for synthesising two or more signals phase-locked to a common reference clock signal are disclosed. In one version, the method comprises steps of generating first and second output signals phase-locked to a reference clock signal, using first and second phase-locked loop circuits. In response to a detected frequency error in the first output signal, the first output signal is corrected by adjusting a frequency-division ratio in the first phase-locked loop circuit. The second output signal is corrected, separately from the correction to the first output signal, by adjusting a frequency-division ratio in the second phase-locked loop circuit, using an adjustment parameter calculated from the detected frequency error. In another method, the second output signal is generated from a common reference clock signal and frequency of the second output signal is also adjusted by adjusting the reference clock frequency (FREF). Schemes for realising the methods are also disclosed.

EFFECT: generating at least two clock signals from one reference clock signal for separate applications in a communication device.

22 cl, 6 dwg