METHOD FOR TESTABILITY OF REALISATION OF LOGIC CONVERTERS Russian patent published in 2013 - IPC G06F11/00 

FIELD: information technology.

SUBSTANCE: method involves initially obtaining a primary mathematical description of the working law of n-input logic converters in Zhegalkin basis testability logic, designing and realising the schematic diagram of the logic converter from an element - logic 1 generator, r series circuits of (k-1) two-input logic elements with an electronically adjusted logic function, which execute k-argument AND functions, and a series circuit of (r-1) two-input inequivalence elements which execute the working function F_p, wherein the step of designing and realising the schematic diagram of the logic converter further includes (s+1) series circuits of (k-1) two-input logic elements with an electronically adjusted logic function and a series circuit of (s+1) two-input inequivalence elements, which forms an error attribute at the output by performing modulo two convolution of the value of the function F_p, all s additional k-argument conjunctions and an additional n-argument conjunction of inversions of input arguments.

EFFECT: high reliability of testability of logic converters.

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