FIELD: information technologies.
SUBSTANCE: method includes stages, at which a divisor is recorded in parallel into matrix cells on memory elements, the first bit of the quotient becomes equal to the sum of module two of the least significant bit in the first column of the matrix and the first bit of the dividend, other bits of the quotient become equal to zero; the number of units b2 is counted in a vector equal to bit-by-bit logical multiplication of the appropriate bits of the second column of the matrix and bits of the quotient, at the same time the second bit of the quotient becomes equal to the sum of module two for the least significant bit b2 and the second bit of the dividend; similarly, the number of units bi is counted in a vector, which is equal to the bit-by-bit logical multiplication of the appropriate bits of the i column of the matrix and quotient bits, afterwards the sum ci of the vector bi and the vector bi-1 shifted by one bit to the right is calculated, at the same time the i bit of the quotient becomes equal to the sum of module two of the least significant bit ci and the i bit of the dividend, as a result the m-bit quotient of initial numbers will be generated.
EFFECT: increased speed of calculation.
2 dwg
Title | Year | Author | Number |
---|---|---|---|
METHOD OF FACILITATING MULTIPLICATION OF FLOATING-POINT NUMBERS REPRESENTED IN RESIDUE NUMBER SYSTEM | 2012 |
|
RU2500018C1 |
METHOD OF FACILITATING MULTIPLICATION OF FLOATING-POINT NUMBERS REPRESENTED IN RESIDUE NUMBER SYSTEM | 2012 |
|
RU2485574C1 |
MATRIX COMPUTING DEVICE | 0 |
|
SU1034032A1 |
MATRIX DEVICE FOR DIVIDING | 0 |
|
SU1247863A1 |
MATRIX COMPUTING DEVICE | 0 |
|
SU1541599A1 |
DIVIDING DEVICE | 0 |
|
SU1282117A1 |
MULTIPLICATION AND DIVISION MATRIX UNIT | 1991 |
|
RU2018932C1 |
DEVICE FOR SQUARING, EXTRACTING SQUARE ROOT, MULTIPLYING AND DIVIDING | 0 |
|
SU1059571A1 |
DIVIDER | 0 |
|
SU1681303A1 |
POLYFUNCTIONAL CALCULATING DEVICE | 0 |
|
SU1293727A1 |
Authors
Dates
2013-11-10—Published
2012-07-27—Filed