METHOD OF FORMING S-BLOCKS WITH MINIMUM NUMBER OF LOGIC ELEMENTS Russian patent published in 2016 - IPC H04L9/06 G09C1/04 

FIELD: physics, computer engineering.

SUBSTANCE: invention relates to computer engineering and cryptography, and particularly to methods of forming S-blocks with a minimum number of logic elements for subsequent implementation in devices for protecting data using cryptographic methods. The method comprises: based on a given S-block, constructing a system of Boolean functions in the form of truth tables; multiplying a 2ⁿ×2ⁿ binary matrix by a Boolean function value; obtaining a system of Zhegalkin polynomials; at the analysis step, determining data for minimisation, and at the synthesis step, obtaining the resultant logic circuit for implementing the S-block, followed by hardware implementation of the circuit based on different integrated microcircuits, including programmable logic devices.

EFFECT: low circuit design costs when implementing an S-block by minimising the resultant logic circuit.

8 dwg, 5 tbl