FIELD: communication.
SUBSTANCE: invention relates to synthesizers based on phase automatic frequency control loop (PLL). For production of radio-frequency signal, signal of frequency Fsync is obtained, and with this signal first microcircuit of direct digital synthesis is clocked in order to obtain reference signal with frequency Fdds1=α1Fsync. Phases and frequencies of reference and synchronised signals are compared to generate analogue voltage proportional to phase and/or frequency mismatch, voltage obtained is filtered at low frequency, and this voltage is supplied to voltage-controlled generator, in order to produce at its output signal with frequency Fout. Part of obtained signal is derived into negative feedback loop for its frequency conversion with subsequent supply of converted signal as synchronised one to phase-frequency detector. Frequency transformation is performed by means of second microcircuit of direct digital synthesis, which is clocked with signal of frequency Fout-DFsync, obtained by mixing of signals with frequencies Fout and DFsync with further separation of differential component in order to produce signal with frequency Fdds2=α2(Fout-DFsync) at its output, where D is frequency division factor for clocking first microcircuit of direct digital synthesis. Note here that factors α1 and α2 are selected based on not fitting into predetermined "prohibited" values fields.
EFFECT: technical result consists in reduction of level of unwanted discrete components in output radio-frequency signal while reducing level of phase noise.
2 cl, 3 dwg
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Authors
Dates
2016-04-10—Published
2015-06-01—Filed