FIELD: radio engineering.
SUBSTANCE: invention relates to synthesizers based on phase-locked-loop frequency control. Method for obtaining a radio frequency signal includes clocking the first chip of direct digital synthesis using a signal of frequency Fsyncr for obtaining the reference signal Fdds1=α1Fsyncr; branching a part of the signal Fout, obtained at the output of a voltage-controlled generator, into the negative feedback loop for its frequency conversion, which is carried out with the help of a second direct digital synthesis chip, clocking it with a signal of frequency Fout-DFsyncr, to obtain on its output a signal of frequency Fdds2=α2(Fout-DFsyncr), where α1 and α2 – are the coefficients that are chosen, based on the condition of their non-occurrence in the predefined "forbidden" ranges of values, whose conversion in the first and second direct digital synthesis chips respectively results in an output signal with side discrete components of amplitude Anout above permissible Aadditional, where n is the harmonic number of the secondary discrete component of the output signal.
EFFECT: technical result consists in reducing the level of spurious discrete components of the output radio frequency signal while maintaining a sufficiently low level of phase noise.
1 cl, 5 dwg
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Authors
Dates
2018-03-16—Published
2017-06-01—Filed