FIELD: computer equipment.
SUBSTANCE: invention relates to computing and can be used for fault-tolerant parallel implementation of the systems of Boolean functions in the means of cryptographic protection of information. Device contains a memory register, a memory unit for storing the coefficients of a linear numerical polynomial (LNP), a memory block for storing system bases, units for calculating the smallest non-negative number deductions (coefficient of LNP) based on system bases, multipliers, multi-adders, masking operator, block of memory of system modules, blocks of memory of orthogonal bases, multi-place adder according to the system module, control and monitoring unit.
EFFECT: technical result is to provide fault tolerance when calculating binary pseudo-random sequences identical to pseudo-random sequences obtained by means of classical generators on linear recurrent shift registers.
1 cl, 3 dwg, 1 tbl
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Authors
Dates
2019-02-14—Published
2018-04-25—Filed