LOW VOLTAGE D-FLIP-FLOP WITH ASYNCHRONOUS VALUE SETTING BASED ON EMITTER-COUPLED LOGIC Russian patent published in 2019 - IPC H03K19/13 

FIELD: electrical engineering.

SUBSTANCE: invention relates to the field of pulse technology. Low-voltage D-flip-flop is proposed, which consists of a single level of differential stages and resistors, forming a driving and driven triggers, synchronized in level. Driving and driven triggers consist of a pair of transistors with combined emitters of the first differential stage, amplifying the input signal, pairs of transistors with combined emitters of the second differential stage with positive feedback formed by connecting the base to the collector of the opposing transistor, allowing to hold the logic value reinforced by the first differential stage, and three resistors.

EFFECT: technical result consists in the possibility of applying the circuit at a supply voltage below 5 V, eliminating additional bias circuits of logical equations, reducing the input capacity of the reset output terminal RST or setting the stored SET value, reducing the input dependence of the forward CLK capacitance and the inverse input of the clock signal CLK, reducing the number of transistors used in the circuit.

1 cl, 3 dwg