METHOD FOR SCHEDULING LOAD DISTRIBUTION OF PROCESSORS IN A COMPUTING SYSTEM Russian patent published in 2020 - IPC G06F9/50 

FIELD: computer equipment.

SUBSTANCE: invention relates to computer engineering. Disclosed is a method for scheduling load distribution of processors in a computer system, which continuously monitors all processors of the system to determine their activity by detecting faults and the processor loses status of active, if it satisfies a failure condition: unavailable or overloaded, wherein the following additional actions are introduced: each processor, which is part of the computer system, executes an independent program, all characteristics of the computing process of each processor, at certain fixed time intervals, are transmitted to the input of the manager, dispatcher, which can be a more powerful processor or server, monitors their operation, a diagnostic (control) program is periodically started in the dispatcher for determining the state of each processor: loading degree, program execution time and other states, wherein each processor generates internal conformity or non-compliance signals of the correct operation, which are transmitted to the dispatcher, upon receipt of the mismatch signal, the dispatcher determines from which processor the signal has come and to which state it corresponds: fault, emergency stop, exceeded the predetermined program execution time, failure in operation or memory deficiency, after receipt of mismatch signal controller determines which processor is less loaded and possibility of load redistribution between other processors, besides, dispatcher after certain time interval performs all polls of all processors for load, processor loses status of active, if it satisfies failure condition: unavailable or overloaded, this information is entered into dispatcher's database, wherein during operation of system in each processor at certain predetermined time intervals there is a subprogram of storing intermediate results of program execution, results of program execution at a given moment in time of each processor are stored and sent to memory dispatcher; in case of failure as a result of failures, the last stored intermediate results of program execution, which were recorded in base of intermediate results for this processor, are transmitted to another less loaded processor of system or, if all processors are loaded, to additional backup processor, which may be provided in system; wherein if the standby processor is not busy with execution of the program, the process of executing the faulty processor program continues in the standby mode; if the standby processor is busy with the execution of the program, the process of executing the faulty processor program continues in the manager; after eliminating the mismatch signal received from the corresponding processor, the controller turns it into active status and system operation continues.

EFFECT: technical result is provision of load distribution between processors in computer system.

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