FIELD: radio engineering.
SUBSTANCE: invention relates to the field of radio engineering, can be used in devices for receiving digital information signals for coherent digital demodulation of binary signals with relative phase shift keying. A digital coherent signal demodulator with binary relative phase shift keying contains an analog-to-digital converter (1), a receiving device (2), a clock pulse generator (3), a register (4) for shifting multi-bit codes for two samples, a subtractor (5), n sample processing units 6-1, 6-2, ... , 6-n (SPU), a register of a shift of multi-digit codes for N samples (9), a calculator of the modulus of the sum (10), a calculator of the modulus of the difference (11), an additional subtractor (12) and a decision block (13). Each SPU consists of an additional shift register of multi-digit codes 7-i and an adder 8-i, where i=1 ... n. The number of n SPU is an integer and depends on the number N of signal periods in the information symbol and is defined as the binary logarithm n=log2N, while the number of processed signal periods is equal to N=2n.
EFFECT: increased noise immunity, elimination of the "reverse operation" error.
1 cl, 7 dwg
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Authors
Dates
2021-06-01—Published
2020-10-09—Filed