APPARATUS FOR MODELLING THE WORK SCHEDULE OF EMPLOYEES OF AN INSTITUTION Russian patent published in 2023 - IPC G06F17/00 G06Q10/06 

FIELD: computing technology.

SUBSTANCE: invention relates to means of modelling optimal work schedules of employees. Apparatus for modelling the work schedule of employees of an institution comprises a clock pulse generator 22 (GTI 22), the output whereof is linked with the first input of the first element AND 26, a first delay element 23, a second delay element 24, a third delay element 17, a group of first registers 8₁...8_n, an (m·n) trigger matrix 1_ij, an (m·n) matrix of second elements AND 2_ij, m groups of third elements AND 21₁, ..., 21_m, a group of first adders 6₁...6_n, a group of first comparison circuits 7₁...7_n, a fourth element AND 13, a group of counters 3₁...3_m, m groups of fifth elements AND 20₁...20_m, a group of second registers 19₁...19_m, a second adder 15, a second comparison circuit 16, m groups of third comparison circuits 4₁...4_m, a third adder 9, a third register 18, a fourth register 10, a group of sixth elements AND 14, a seventh element AND 25, the input of the counter 3₁ is connected to the output of the first element AND 26, the output of each trigger 1_ij, (i=1...m, j=1...n) is connected to the first input of the like group of second elements AND 2_ij, the second input whereof is connected to the first element AND 26 via the second delay element 24, the third input of the second element AND 2_ij is connected to the output of the like counter 3_i, and the output is connected to the like input of the first adder 6_j (j=1, ..., n), the output whereof is connected to the first input of the like first comparison circuit 7_j, the second input whereof is connected to the output of the like first register 8_j, the output of each first comparison circuit 7_j (j=1, ..., n) is connected to the like input of the fourth element AND 13, the output whereof is connected to the first inputs of the groups of third elements AND 21_i (i=1...m), the output of the counter 3_i is connected to the second input of the third elements AND 21_i (i=1...m), the output whereof is connected to the first input of the like group of fifth elements AND 20_i and to the like input of the second adder 15, the output whereof is connected to the first input of the group of sixth elements AND 14 and to the first input of the second comparison circuit 16, the second input whereof is connected to the output of the third register 18 and the output is connected via the third delay element 17 to the second inputs of the groups of fifth elements AND 20_i and to the second input of the group of sixth elements AND 14, the output whereof is connected to the second input of the third register 18, the output of each group of fifth elements AND 20_i (i=1...m) is connected to the input of the second registers 19_i, the outputs of each whereof are first outputs 29 _i of the apparatus, the output of the seventh element AND 25 is connected to the second inverse input of the first element AND 26 and is the second output 28 of the apparatus, the first input of the group of third comparison circuits 4_i is connected to the output of the like counter 3_i (i=1...m), the second input is connected to the output of the fourth register 10, and the output is connected to the second input of the like counter 3_i as an overflow signal, to the input of the next counter 3_i (i=1...(m-1)) and to the like inputs of the seventh element AND 25, the input of the fourth register 10 is connected to the output of the third adder 9, the inputs whereof are connected to the like outputs of the first registers 8₁...8_n, the control input of the adder 9 is connected to the input 27 of the apparatus, the input 27 of the apparatus is connected via the first delay element 23 to the third input of the first element AND 26; included are a minimal code selection unit (BVMC) 11, a fifth register 12, m groups of eighth elements AND 5_i (i=1,..., m), the outputs of the first registers 8_j (j=1, ..., n) are connected to the like inputs of the BVMC 11, the control input whereof is connected to the input 27 of the apparatus and the output is connected to the input of the fifth register 12, the output whereof is connected to the first inputs of the groups of eighth elements AND 5_i (i=1,..., m), the second input whereof is connected to the output of the comparison circuit 4_i (i=1,..., m) and the output is connected to the third input of the counter 3_i (i=1,..., m).

EFFECT: reduced time for determining the optimal work schedules of employees.

1 cl, 1 dwg, 1 tbl