FIELD: digital signal processing.
SUBSTANCE: device comprises two n/2-bit shift registers, a quotient and remainder generation unit, while the quotient and remainder formation unit comprise three comparison units, a multiplexer, an OR gate, an adder, a remainder code register, two n/2-bit shift registers, the multiplexer comprises two inverters, two AND gates, three keys, a block of OR gates, two OR gates, n is the number of digits in the representation of numbers.
EFFECT: increasing the speed of the formation of the remainder of the modulo number and the incomplete quotient.
1 cl, 3 dwg, 2 tbl
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Authors
Dates
2023-06-26—Published
2023-03-01—Filed