FIELD: computer technology. SUBSTANCE: device has storage 3, signal mating units 4-6, evenness address checking unit 7, evenness data checking unit 8 which has inputs connected with device data bus 2, the first and the second NON-EQUIVALENCE the first and the second gates 9 and 10. Unit 8 and NON-EQUIVALENCE gate 9 are used for data modulo 2 convolution as when recording and when reading out. For that purpose outputs of storage 3 are connected to inputs of unit 8 through unit 6. When information is in process of recording the address and data which enter address input 1 and data bus 2 correspondingly, have to be convoluted in units 7, 8 and in NON-EQUIVALENCE gate 9 into address and data resulting evenness bit which is recorded into storage 3. When reading address and data evenness bit being formed in the output of NON-EQUIVALENCE gate 9 is compared with bit of evenness formed when information has been recorded. Comparison is carried out in out unit 10 which has output 12 to generate signal of error availability if noncoincidence is observed. EFFECT: simplified design. 1 dwg
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Authors
Dates
1994-03-30—Published
1986-12-18—Filed