FIELD: computer technology. SUBSTANCE: memory control unit has central control unit, bus former, unit for mating with on-line storage, data address control unit, which has address register, two decoders, physical address storage, recording unit, two control units. Data address sing control unit, data buffer memory control unit, data buffer memory are brought into the device additionally. Data address control units has two bus formers, ageing unit, substitution unit, read-out and comparison unit, two registers, two multiplexers, unit of AND gates, adder, read-out unit. Data address sing control unit has data register, read-out/record and comparison unit, control unit, storage, substitution unit, modulo 2 adder, address register, column number decoder, line number decoder, control unit. EFFECT: improved efficiency. 52 dwg
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Authors
Dates
1994-03-30—Published
1991-10-28—Filed