FIELD: information technology.
SUBSTANCE: device includes the control unit, the writing synchronising clock, the reading synchronising clock, the read-write channels, the first OR element, the writing amplifier connected to the writing head, the reading head connected to the shaping circuit through the reading amplifier, the second OR element, the multiplexor, the third OR element, the second, third and fourth AND elements, the decoder, and the coder. Each channel's coder input is connected to the information source, while the output is connected to one of the AND element's inputs. Another AND element's input is connected to one of the inputs of the control unit and to one input of another AND element, while the output is connected to one of the second OR element's inputs. Another OR element's input is connected to the output of the third AND element, which is connected to the shaping circuit with one input and to another output of the control unit with another input, and to one of the fourth AND element's inputs. The output of the second OR element is connected to the information input of the multiplexor whose setup inputs are connected to the counter outputs.The counter input is connected to the output of the first OR element, one of whose inputs is connected to the writing synchronising clock, another - to the reading synchronising clock. One of the multiplexor outputs is connected to one of the third OR element's inputs. Every other multiplexor's input is connected to the respective another OR element's input in all other read-write channels. The output of the third OR element in each channel is connected to another input of the second AND element and to another input of the fourth AND element. The second AND element's output is connected to the writing amplifier, the fourth AND element's output is connected to the decoder whose output is connected to the output information data bus.
EFFECT: reducing the reading inaccuracy.
2 dwg
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Authors
Dates
2008-07-27—Published
1986-04-25—Filed