FIELD: computer engineering. SUBSTANCE: device has argument code input 1, high bit determination unit 2, encoder 3, shift unit 4, adder 5, multipliers 7-10, subtracters 11, 12, accumulating adder 13, code inputs 14, 15, 16, 17 device synchronization input 18. Outputs of encoder 3 and adder 4 are device outputs 6. Precision of computing of logarithm to base 2 is increased by use of fractional rational expression approximating logarithm mantissa and iterating computation of this expression. Four multipliers, two subtracters, accumulating adder and new functional connections are introduced to accomplish the goal of invention. Proposed invention is determined by the following features. Algorithm of operations is determined by solving of iterating equation in contrast to calculation of logarithm table proportional parts. Logarithm mantissa is determined by fractional rational approximation over full range of mantissa variation and not by linear functions each of which correspond to its own range. EFFECT: increased precision. 4 dwg
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Authors
Dates
1994-01-30—Published
1991-04-02—Filed