FIELD: computer engineering. SUBSTANCE: device has n computing units and 2n input units. Each computing unit has for types of computing units which process bits of data. Each input unit has delay units which delay i-th bit of each number for i+1 clock pulse. Two-level systolic model of data processing is used for words as well as for bits. This results in increased efficiency of hardware use and increased speed of device. EFFECT: increased speed. 7 cl, 9 dwg, 2 tbl
Title | Year | Author | Number |
---|---|---|---|
DEVICE FOR COMPUTATION OF EIGENVALUES OF (N X N) MATRIX | 1992 |
|
RU2012050C1 |
DEVICE FOR MULTIPLYING THREE MATRICES | 1990 |
|
RU2024933C1 |
DEVICE FOR MULTIPLYING MATRIXES | 1991 |
|
RU2011221C1 |
MATRIX MULTIPLIER | 1990 |
|
SU1779180A1 |
MATRIX INVERSION DEVICE | 1989 |
|
SU1819020A1 |
DEVICE FOR INVERTING N X N MATRICES | 1990 |
|
RU2037199C1 |
DEVICE WHICH SOLVES SYSTEMS OF LINEAR ALGEBRAIC EQUATIONS | 1994 |
|
RU2116667C1 |
DEVICE FOR SOLVING SETS OF LINEAR ALGEBRAIC EQUATIONS | 1989 |
|
SU1819019A1 |
DEVICE FOR SOLVING SYSTEMS OF LINEAR ALGEBRAIC EQUATIONS | 1990 |
|
RU2037197C1 |
DEVICE FOR SOLUTION OF SYSTEM OF LINEAR ALGEBRAIC EQUATIONS | 1991 |
|
RU2012049C1 |
Authors
Dates
1994-04-15—Published
1991-07-03—Filed