FIELD: computer engineering. SUBSTANCE: interface unit of device has read-only memory unit (ROM), control register, buffer register, failure flip-flop, decoder, second counter, AND gate, unit of AND-OR gates, OR gate, delay gate, pulse generator and corresponding connections. This results in possibility to switch off users and their interface units if user exceeds time limit or fails. This also results in possibility to generate control signals for switching off other users by given interface unit. Each pulse generated by control unit causes lock of control bus by only one interface unit according to serial number of pulse if priority code equals to current code. When user is serviced (information bits are transmitted through interface unit), connection of other users (their interface unit lock control bus) is impossible. Interface unit of current user is switched off according to program implemented as microprograms stored in ROM when receiving-transmitting session ends, when time slice provided for information transfer to this user ends, when errors cause increased service time. EFFECT: increased reliability, increased efficiency. 2 dwg
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Authors
Dates
1994-07-30—Published
1991-08-05—Filed