MODULO 7 ADDER Russian patent published in 1994 - IPC

FIELD: computer technology; microelectronics. SUBSTANCE: adder has four half adders, single-digit binary adder, two OR gates, two AND gates, modulo 2 two addition elements, inputs of senior, mean and junior digits of the first and the second operands, outputs of senior, mean and junior digits of the result. Senior, mean and junior digits x₁, x₂ and x₃ correspondingly of the first operand X=4x₁+2x₂+x₃ enter inputs of the device, as well as senior, mean and junior digits y₁, y₂ and y₃ of the second operand Y =4y₁+2y₂+y₃. Values of sensor, mean and junior result digits r₁, r₂ and r₃ correspondingly (input operand modulo 7 sum) are formed at outputs of the device R = (X+Y) mod7 = 4r₁+2r₂+r₃. In this case x_j is equal to {0,1}, y_j equals to {0,1}, and r_j ({0,1}, 0≅ X≅ 7, 0≅ Y≅ 7, 0≅ R≅ 7, j = 1,3. EFFECT: improved efficiency. 1 tbl, 1 dwg