MODULO-SEVEN ADDER Russian patent published in 1995 - IPC

FIELD: computer engineering and microelectronics. SUBSTANCE: adder has nine equivalence gates, three modulo-two sum gates, inputs of high-, medium-, and low-order bits of first and second operands, outputs of high-, medium-, and low-order bits of result. Modulo-seven adder functions as follows. High-order bit x1, medium-order bit x2, and low-order bit x3 of first operand X=4x1+2x2+x3 as well as high-order bit y1, medium-order bit y2, and low-order bit y3 of second operand Y=4y+2y2+y3 arrive at inputs. Values of high-order bit r1, medium order bit r2, and low-order bit r3 of result (modulo-seven sum of input operands) R=(X+Y)mod7=4r1+2r+2+r3 are shaped across outputs. Here we have x_i∈ 10{0,1} y_i ∈{0,1} r_i∈ {0,1} 0 ≅ X ≅ 7, O ≅ Y ≅ 7, O ≅ R ≅ 7. EFFECT: enlarged functional capabilities. 1 dwg, 1 tbl