FIELD: storages on the base of bipolar transistors. SUBSTANCE: couplings between transistors of communication 3 and 4 and load resistors 5 and 6 of buffer element 2 are changed. As a result, delaying influence of process of switching of voltages may be reduced of inputs 7,8 of sample due to reduction in changes in voltages in the units. Process of forming of output information signal may be accelerated due to introduction of trigger threshold principle of operation of buffer element 2. Difference in potentials between base of closed switch transistor 12, 13 of selected memory cell 1 and base of corresponding communication transistor 3, 4 may be improved. Storage also has resistors 14, 15 and has vocabulary sample inputs 9, control inputs 10, 11 and inputs 16 of store current. EFFECT: improved speed of operation; improved noise immunity and reliability of array storage. 4 dwg
Title | Year | Author | Number |
---|---|---|---|
MEMORY | 1991 |
|
RU2018979C1 |
GENERATOR OF WRITE PULSES FOR MEMORY UNIT | 1994 |
|
RU2097843C1 |
MEMORY DEVICE | 0 |
|
SU1751816A1 |
STORAGE | 0 |
|
SU1751814A1 |
TRIPLE-STATE OUTPUT CIRCUIT | 1992 |
|
RU2072629C1 |
WRITE/READ AMPLIFIER | 0 |
|
SU1437913A1 |
STORAGE | 0 |
|
SU1536442A1 |
STORAGE | 0 |
|
SU1656595A1 |
ON-LINE MEMORY DEVICE | 0 |
|
SU1573472A1 |
STORAGE FOR RANDOM-ACCESS MEMORY | 0 |
|
SU1751815A1 |
Authors
Dates
1994-09-30—Published
1991-04-19—Filed