FIELD: memories. SUBSTANCE: proposed invention consists in changes of connections of transistors with the purpose to increase logical differences in readout mode and to exclude influence of transients upon memory access delay. In addition to mentioned components, the device has also several resistors. EFFECT: improved speed of response and noise immunity of memory. 3 dwg
Title | Year | Author | Number |
---|---|---|---|
DATA STORAGE | 1991 |
|
RU2020614C1 |
GENERATOR OF WRITE PULSES FOR MEMORY UNIT | 1994 |
|
RU2097843C1 |
MEMORY DEVICE | 0 |
|
SU1751816A1 |
STORAGE | 0 |
|
SU1751814A1 |
TRIPLE-STATE OUTPUT CIRCUIT | 1992 |
|
RU2072629C1 |
STORAGE FOR RANDOM-ACCESS MEMORY | 0 |
|
SU1751815A1 |
CMOS GATE LEVEL CONVERTER | 1994 |
|
RU2097914C1 |
WRITE/READ AMPLIFIER | 0 |
|
SU1437913A1 |
MATRIX MEMORY | 0 |
|
SU1343443A1 |
MEMORY DEVICE | 0 |
|
SU1361630A1 |
Authors
Dates
1994-08-30—Published
1991-04-22—Filed