MULTIPLIER Russian patent published in 1994 - IPC

FIELD: computer engineering. SUBSTANCE: device can operate both as three independent n-bit accumulators or as three independent n-bit multipliers. In multiplication (addition) mode, multiplicands (addends) are entered in registers 1-3 and multiplier (unit vector), in registers 4-6. Then operands go via groups of AND gates 7-9, delay units 10-12, and n multiplexor units 13 to first group of n systolic half-adders 14 and second group of n systolic half-adders 15 where unknown sums and products are computed. Sums and products are computed in device by executing operations over cubic coverings of carry function and sum function which are written earlier, during programming mode, in first and second groups of systolic half-adders 14 and 15, respectively. EFFECT: enlarged functional capabilities of device due to provision for its operation as multiplier and as adder, facilitated accumulating procedures, and interchangeability of its units. 4 cl, 9 dwg, 1 tbl