FIELD: electronic engineering. SUBSTANCE: accumulator incorporating array of m lines and n columns of MIS transistors, each connected in series with break down-programmable capacitor, m address buses connected to line decoder, and n bit buses connected to column decoder, transistor gates in each line being connected to address bus of given line, transistor drains of each column connected to bit bus of given column, has one of plates of each capacitor connected to source of respective transistor and second plates of capacitors are combined and connected to auxiliary bus connected to programming voltage source. EFFECT: simplified programming procedure, improved speed of response due to reduced capacity of bit buses. 2 dwg
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Authors
Dates
1995-02-09—Published
1991-05-30—Filed