FIELD: pulse technique. SUBSTANCE: noise-immune pulse counter has reset bus 1, count pulse bus 2, power bus 3 for inverters and followers, and in each bit place it has flip-flop 4 (4-1, 4-2, 4-3, 4-4), first resistor 5 ( 5-1, 5-2, 5-3, 5-4), second resistor 6 ( 6-1, 6-2, 6-3, 6-4), storage element 7 (7-1, 7-2, 7-3, 7-4), built around rectangular hysteresis loop core carrying read and write windings, in each place except for last one it has first EXCLUSIVE OR gate 8 (8-1, 8-2, 8-3) and second EXCLUSIVE OR gate 9 (9-1, 9-2, 9-3); in each bit place it has half-adder 10 (10-1, 10-2, 10-3, 10-4), inventor 11 (11-1, 11-2, 11-3, 11-4), and follower 12 (12-1, 12-2, 12-3, 12-4). Flip-flop 4 (4-1, 4-2, 4-3, 4-4) is essentially asynchronous RS flip-flop. EFFECT: improved noise immunity. 1 dwg
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Authors
Dates
1995-06-27—Published
1991-06-28—Filed