CONTROLLED TIMER Russian patent published in 1995 - IPC

Abstract RU 2037872 C1

FIELD: automation and computer engineering. SUBSTANCE: device has first, second and third control wires 1, 2, 3, Wire 1 is connected to cathode of diode 4 and to anodes of diodes 5 and 6. Wire 2 is connected to cathode of diode 7 and to anodes of diode 8, 9. Wire 3 is connected to anode of diode 10. Cathode of diode 5 is connected to input of pulse shaper 12 and through resistor 13 to common wire 11. Cathode of diode 8 is connected to input of pulse shaper 14 and through resistor 16 to common wire 11. Cathodes of diodes 6, 9, 10 are connected to one another and are also connected to input of secondary power supply 18 through resistor 17. Input of secondary power supply 18 is connected through capacitor 19 to common wire 11, output of secondary power supply 18 is connected to input of initial settings circuit 20 and to power supply inputs of pulse shapers 12, 14, 15, output of pulse shaper 12 is connected to input of pulse shaper 21, first input of AND gate 22 and to second input of XOR gate 23. Output of pulse shaper 14 is connected to first input of AND gate 24 and to second input of XOR gate 23. Output of initial setting circuit 20 is connected to input of pulse shaper 25 and to zero setting input of Gray-code counter 26. Output of pulse shaper 21 is connected to second input of AND gate 24, which output is connected to first input of OR gate 27. Output of pulse shaper 25 is connected to second input of AND gate 22 and clock input of flip- flop 28. Output of AND gate 22 is connected to second input of OR gate 27 and through delay gate 29 to reading permission input of memory unit 30. Output of OR gate 27 is connected to write permission input of memory unit 30. Output of XOR gate 23 is connected to zero setting input of rate scaling circuit 31 and first input of OR gate 32. Second input of OR gate 32 is connected to output of rate scaling circuit 31, and output of OR gate 32 is connected to counting input of counter 26. Information input of rate scaling circuit 31 is connected to output of driving oscillator 33, information input of flip-flop 28 is connected to output of modulo- two folding unit 34, which outputs are connected to corresponding bit inputs of counter 26. Output of flip-flop 28 is connected to strobe input of decoder 35 which inputs are connected to high-order bit outputs 36 of counter 26. They are also connected to information inputs of memory unit 30. Output of decoder 35 is connected to input of pulse shaper 15. This output also serves as timer output. Ones setting high-order bit inputs of counter are connected to corresponding outputs of memory unit 30. EFFECT: decreased number of control wires. 2 dwg

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RU 2 037 872 C1

Authors

Dikarev I.I.

Shishkin G.I.

Dates

1995-06-19Published

1990-07-17Filed