FIELD: computer engineering. SUBSTANCE: memory cell has core with rectangular hysteresis loop and winding whose first lead is connected to output of first logic element in the form of NAND gate one of whose inputs is connected to magnetic reversal bus, flip-flop whose R input is connected to reset bus and inverted output, to one of inputs of second logic element, resistor one of whose leads is connected to power bus, and data bus; novelty is that in addition it is provided with newly introduced resistor, transistor, and diode, that second logic element is made in the form of EXCLUSIVE OR gate, flip-flop, in the form of asynchronous RS flip-flop built around NAND gates, and that other input of second logic element is connected to bus and its output, to other input of NAND gate and through additional resistor, to second lead of core winding, cathode of diode, and base of transistor whose collector is connected to other lead of resistor and to S input of flip-flop and emitter is connected to diode anode and to first lead of core winding. EFFECT: reduced power requirement and improved noise immunity. qE
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Authors
Dates
1998-09-27—Published
1990-12-06—Filed