FIELD: automation and computer engineering. SUBSTANCE: device has three (n+1) bit input registers which are connected to inputs of group of n majority elements and to corresponding inputs of three groups of n "EQUAL" gates which outputs are connected to corresponding inputs of first, second and third AND gates, outputs of first second and third AND gates are connected to inputs of first OR gate which output is connected to control input of n-channel commutator which inputs are connected to corresponding outputs of group of majority gates. Inverse output of first OR gate is connected to input of second OR gate which output is connected to delay gate. (n+1) bits of input registers are connected to corresponding inputs of fifth, sixth and seventh AND gates which outputs are connected to corresponding inputs of third AND gate which inverse output is connected to second input of second AND gate. EFFECT: increased reliability of output signal generation. 1 dwg, 2 tbl
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Authors
Dates
1995-07-20—Published
1990-07-09—Filed