ELECTRONIC CLOCK TIME SCALE PHASER Russian patent published in 1997 - IPC

FIELD: instrumentation engineering; phasing out time scales of off-line devices. SUBSTANCE: phaser has master oscillator, delay line, first switch, first and second counters, biconditional gate, discriminator built up of four NAND gates, control unit assembled of OR gates, first and second D flip-flops, first and second logic adders, group of AND gates, group of (m+1) AND gates and RS flip-flop, shaper, first inverter, second and third switches, arithmetic unit, main storage. Control unit is provided, in addition, with second inverter, third and fourth D flip-flops whose D inputs are connected to phases common bus, inverted output of fourth D flip-flop functions as second output of control unit and is connected to second control inputs of second and third switches whose first control inputs are connected to first output of control unit which is, essentially, direct output of third flip-flop whose inverted output is connected to C input of fourth D flip-flop and functions as fourth output of control device; C input is connected to output of second inverter whose input is connected to S input of fourth D flip-flop and to AND gate output; S input of third D flip-flop is connected to first input of OR gate and functions as third input of control device; OR gate output is connected to S inputs of first and second D flop-flops. EFFECT: improved accuracy of time scale phasing. 5 dwg