ADDER Russian patent published in 1997 - IPC

Abstract RU 2092891 C1

FIELD: automation and computer engineering. SUBSTANCE: device has converter 1 from binary to compressed code, AND gates group 2, halving unit 3 which uses compressed code and outputs position code, delay gates group 4, encoder 12. Next bit of sum is generated at device output 10. Result is calculated for n cock cycles where n is bit length of terms. EFFECT: increased speed. 1 dwg

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RU 2 092 891 C1

Authors

Kim P.A.

Dates

1997-10-10—Published

1994-10-27—Filed