FIELD: automation. SUBSTANCE: time delay is set as code word which enters to address line 1 before input command enters "counting start" line 12. In writing mode first region of read-only memory unit 4 is accessed and number N1 which correspond to delay time is stored in memory unit 9 using code words of address line 1. In counting mode output information of memory unit 9 is used for access to second region of data array of read-only memory unit 4 which stores algorithm for increment of input number N1 by step 1. Process of addition with clock frequency f which is set by pulse oscillator 13 continues until code combination M of decoder 10 is reached. If condition N1+ n =M, is satisfied, decoder 10 generates execution command. Two multiplexers 2 and 3, two read-only memory units 4 and 5, two comparison circuits 6 and 7 provide continuous validity check of operations of basic nodes of system and prevention of immature output signal. EFFECT: increased reliability. 2 cl, 2 dwg
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Authors
Dates
1997-11-27—Published
1994-12-20—Filed