PARALLEL ASYNCHRONOUS ADDER Russian patent published in 1997 - IPC

FIELD: computer engineering. SUBSTANCE: device has n units 6.1-6.n for parallel processing of cut-off bits, n-1 pulse generators 7.1-7.n, starting pulse generator 7.0, NOR gate 8. Each unit 6 has four gates 1-4 which has high resistance inputs, and arithmetic half-adder 5. Specific feature of parallel asynchronous adder is algorithm of addition of operands for cut-off bits. Feedback of output of sum of arithmetic half-adder to its input through one gate provides separation of situation of carries and their simultaneous correction in different places of parallel adder. EFFECT: increased speed. 3 dwg