FIELD: communication equipment. SUBSTANCE: device has four read-only memory units 1-4, multiplexer, inverter, three NOR gates 7, 8, 9, and equality gate 6. Inputs of digital adder receive two eight-bit parallel digital codes which high bit carries sign information, three next bit carry information about code values (code segments), four lower bits carry information which determines code values (code steps). Device outputs parallel eight-bit code of same structure as at inputs. EFFECT: increased precision of adding of digital parallel codes. 5 dwg , 1 tbl
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Authors
Dates
1997-12-20—Published
1994-09-30—Filed