FIELD: communications engineering; digital signal transmission to obtain multiplexed signal and to synchronize multiplexed receive signal with it. SUBSTANCE: digital signals of same level in plesiochrono-digital hierarchy have only approximately equal clock frequencies and therefore, they must be subjected to plesiochronous processing. However, synchronous interaction between transmitted and received multiplexed signals is necessary. This can be ensured if auxiliary groups are created in transmitting and receiving parts of device at which zero bits (LB) are skipped between data bytes (SD). These zero bits are eliminated by means of series- parallel conversion, storage and series-parallel conversion with aid of auxiliary clock signal Th. Receive clock signal is tuned to transmit signal by introducing or, respectively, eliminating one or more zero bits between two data bytes (SD) on receiving end. Device has on transmitting end A series-parallel code converter 1, parallel register 2, parallel-series code converter 3, first and second frequency dividers 5,4 frame-synchronization signal shaper unit 6, auxiliary clock generator 7; on receiving end B, it has frame- synchronization signal separating unit 8, clock frequency recovery unit 9, second frequency divider 10, series- parallel code converter 11, parallel register 12, parallel-series code converter 13, first frequency divider 14, phase adjustment unit 15. EFFECT: improved reliability of digital signal transmission and reception. 5 cl, 5 dwg
