FIELD: automation and computer engineering, in particular, design of control and computational systems, and logical control systems of multilevel hierarchical automatic control systems. SUBSTANCE: device has microprogram memory unit, microprogram register, address register, multiplexer of logical conditions, buffer memory unit, two constant generators, comparison circuit, starting flip-flop, address commutator, two clock oscillators, output commutator, flip- flop, five AND gates, five OR gates, three delay gates, decoder of synchronization node number, three groups of AND gates and two groups of OR gates. EFFECT: increased speed of synchronization of parallel microprogram code pieces due to minimization of interval between completion of parallel code pieces and generation of respective feature signal, simplified design. 5 dwg
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Authors
Dates
2000-06-20—Published
1999-02-25—Filed