FIELD: communication systems. SUBSTANCE: proposed interleaving method and device are designed to generate address for interleavers of different sizes using single algorithm include following procedures: sequential storage of N input bit characters in memory at address of 0 to (N 1), generation of first variable m and second variable J meeting equation N = 2mxJ, and read-out of Kth (0≤K≤(N-1)) bit character at address defined by 2m(K mod J)+BRO(K/J) equation, where BRO is function for binary-to-decimal value conversion by bits reversal. EFFECT: enlarged functional capabilities. 10 cl, 3 dwg, 4 tbl
