FIELD: communications engineering.
SUBSTANCE: proposed interleaving device and method are designed for evaluating new size N' = 2mx(j + 1) of interleaver and addresses from 0 to N - 1 in case desired size N of interleaver is greater than 2mxj and smaller than 2mx(j + 1), where m is first parameter pointing to number of serial zero bits from least significant bit (LSB) to most significant bit (MSB); j is second parameter corresponding to decimal value of bits other than serial zero bits. These interleaving device and method provide for saving N bits of input data in interleaver memory with new interleaver size N' from 0 address to N - 1 address. Then interleaving device and method execute interleaving involving partial bit reversal operations (PBRO) in memory with new interleaver size N' and read data out of memory by erasing addresses corresponding to addresses N to N' - 1 prior to interleaving.
EFFECT: enhanced effectiveness of interleaver memory.
10 cl, 6 dwg, 7 tbl
