FIELD: data processing systems executing arithmetic operations. SUBSTANCE: device has logic processing means and instruction decoder controlling logic processing means that executes data processing operation on first word (operand P of N-bit data) and on second word (operand Q of N- bit data) for generating resultant word R of N-bit data. Method includes following operations: generation of processing control signals, execution of data processing on words or data operands under control of mentioned control signals, generation of control signals to control logic processing means that should execute data processing operation on first word (operand P of N-bit data) and on second word (operand Q of N-bit data) to generate resultant word R (N-bit data). EFFECT: facilitated clocking of multiplying operation within one cycle, reduced memory capacity due to dispensing with assigning saturating versions of more than one multiplying instructions. 15 cl, 4 dwg
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Authors
Dates
2004-03-10—Published
1999-05-26—Filed