COINCIDENCE-ACCUMULATION TYPE ADDER Russian patent published in 2007 - IPC G06F7/50 

FIELD: digital computer engineering.

SUBSTANCE: adder realizes operations of addition, left and right code shift, inversion, modulus two addition, logical addition, multiplication. Each bit of adder contains two RS-triggers, nine AND elements, five OR elements, five NOT elements, eight control buses and information input. Adder features construction of each bit only on basis of two RS-triggers and new circuits for realization of additional operations. Total number of inputs of logical elements of one bit equals 36, in average one realized operation requires about 5 inputs (Quine price).

EFFECT: expanded functional capabilities with minimal hardware costs.

1 dwg, 1 tbl