METHOD AND DEVICE OF CORRECTION OF ANALOG-DIGITAL TRANSFORMATION ERRORS Russian patent published in 2009 - IPC H03M1/10 

FIELD: physics.

SUBSTANCE: method of correction of errors of analogue-digital transformation consists in use of processes of testing (continuous and periodic) and corrections. And mode of continuous testing corrected k-digit ADT, carried out 2^m times, begins with the switch-on point. The test signal represents step function of the voltage identified with 2^m by reference signals, code which equivalent of a serial number serves as address of the random access memory cells (RAM) in which the target code of the tested ADT is registered. During the continuous testing the correction mode is blocked. Then the stage of correction of errors of the analogue-digital transformation, characterised begins alternation of two cycles: analysis of input signal and periodic testing. At correction by effect of analogue-digital transformation of an initial signal the code y₁ is, the code m which senior discharges serves as code of first reference signal U_r1 and the address of meshes of storage of the RAM in which effect of analogue-digital transformation of the first reference signal Y₂ is written down, carried out earlier during testing. Magnification of value of code U_r1 at unity leads to formation of code of second reference signal U_r2 and reading from the RAM cells effect of analogue-digital transformation of the second reference signal Y₃ which has been carried out earlier during testing; the corrected effect of analogue-digital transformation of an initial signal calculate under the formula . The device of embodying of the method of error correction of analogue-digital transformation contains generator of clock impulses (1), k-digit dyadic counter (2), block of guidance (3), two m-element blocks of keys (4, 13), m-digit DAC (5), the circuit changer of the analogue signals (6), corrected k-digit ADT (7), RAM (2^m words × k digit), three k-digit registers of storage (9, 15, 16), calculator (10), m-digit register of storage (11), m-discharge adder (12), block (14) m three-input OR circuits.

EFFECT: decrease in complexity of embodying at simultaneous increase of accuracy and speed.

2 cl, 6 dwg